1. Field of the Invention
The present invention relates to a pattern shape evaluation method, a program, and a semiconductor device manufacturing method.
2. Related Background Art
In evaluating the shape of a pattern, a method is widely employed in various industrial fields in which a reference pattern is prepared as a pattern serving as an evaluation standard for an evaluation target pattern and the shape of the pattern is evaluated using a difference between the reference pattern and the evaluation target pattern as an index. For example, in the evaluation of a semiconductor device pattern, whether or not a processed shape of the device pattern is good is judged by use of a scanning electron microscope (SEM) image as an evaluation image of the pattern and by use of design data as the reference pattern.
In particular, in order to deal with complicated pattern shapes, another method has been proposed which comprises generating a tolerance of a pattern as CAD data, reading the tolerance and then superposing the tolerance on design data to display a tolerance shape pattern targeted for measurement, and superposing edge data for the obtained tolerance shape pattern onto edge data for an evaluation target pattern to judge whether or not the pattern is good (e.g., Japanese Patent Laid Open (kokai) 2005-098885).
To achieve the method described in Japanese Patent Laid Open (kokai) 2005-098885, it is essential to establish a method of generating a tolerance shape pattern effective in the evaluation of the pattern shape as well as a method of accurately superposing the tolerance shape pattern on the edge data. To this end, the document described above has also proposed the provision of the tolerance shape pattern with, in addition to the width and area of a target pattern, the distance from a corner of the target pattern, etc., an upper limit value and a lower limit value which correspond to one of: the distance from at least one side of a contact pattern to one side of a wiring line pattern parallel to the one side of the contact pattern when the contact pattern is connected to the wiring line pattern; and the distance between the wiring line pattern and the contact pattern when the contact pattern is formed adjacently to the wiring line pattern. This enables the generation of a detailed tolerance shape pattern adapted to the characteristics of a device (refer to the tolerance shape pattern in FIG. 3 of this document).
However, the method described in the above document has a disadvantage that much labor is required in the generation of the tolerance shape pattern. The file size of the CAD data incorporating tolerance data runs up to about three times that of ordinary CAD data, and there is thus a problem of an increase in computer resources necessary to save and expand the file. The method described in the above document has another problem that an accurate evaluation of the shape of the evaluation target pattern is not enabled only by the design data for a pattern within a layer where the evaluation target pattern is present, in a product such as a semiconductor device having a layer structure.